Datasheet
ePWM Registers
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34.4.8.5 Digital Compare Filter Offset Register (DCFOFFSET)
Figure 34-95. Digital Compare Filter Offset Register (DCFOFFSET) [offset = 6Ah]
15 0
DCOFFSET
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-55. Digital Compare Filter Offset Register (DCFOFFSET) Field Descriptions
Bit Field Description
15-0 OFFSET Blanking Window Offset
These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when
the blanking window is applied. The blanking window reference is either period or zero as defined by the
DCFCTL[PULSESEL] bit.
This offset register is shadowed and the active register is loaded at the reference point defined by
DCFCTL[PULSESEL]. The offset counter is also initialized and begins to count down when the active
register is loaded. When the counter expires, the blanking window is applied. If the blanking window is
currently active, then the blanking window counter is restarted.
34.4.8.6 Digital Compare Capture Control Register (DCCAPCTL)
Figure 34-96. Digital Compare Capture Control Register (DCCAPCTL) [offset = 68h]
15 8
Reserved
R-0
7 2 1 0
Reserved SHDWMODE CAPE
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-56. Digital Compare Capture Control Register (DCCAPCTL) Field Descriptions
Bit Field Value Description
15-2 Reserved 0 Reserved
1 SHDWMODE TBCTR Counter Capture Shadow Select Mode
0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR =
TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the
DCCAP register will return the shadow register contents.
1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will
always return the active register contents.
0 CAPE TBCTR Counter Capture Enable/Disable
0 Disable the time-base counter capture.
1 Enable the time-base counter capture.
1822
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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