Datasheet

ePWM Registers www.ti.com
34.4.8 Digital Compare Submodule Registers
34.4.8.1 Digital Compare A Control Register (DCACTL)
Figure 34-91. Digital Compare A Control Register (DCACTL) [offset = 62h]
15 10 9 8
Reserved EVT2FRC EVT2SRCSEL
SYNCSEL
R-0 R/W-0 R/W-0
7 4 3 2 1 0
Reserved EVT1SYNCE EVT1SOCE EVT1FRC EVT1SRCSEL
SYNCSEL
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-51. Digital Compare A Control Register (DCACTL) Field Descriptions
Bit Field Value Description
15-10 Reserved 0 Reserved
9 EVT2FRC SYNCSEL DCAEVT2 Force Synchronization Signal Select
0 Source Is Synchronous Signal
1 Source Is Asynchronous Signal
8 EVT2SRCSEL DCAEVT2 Source Signal Select
0 Source Is DCAEVT2 Signal
1 Source Is DCEVTFILT Signal
7-4 Reserved 0 Reserved
3 EVT1SYNCE DCAEVT1 SYNC, Enable/Disable
0 SYNC Generation Disabled
1 SYNC Generation Enabled
2 EVT1SOCE DCAEVT1 SOC, Enable/Disable
0 SOC Generation Disabled
1 SOC Generation Enabled
1 EVT1FRC SYNCSEL DCAEVT1 Force Synchronization Signal Select
0 Source Is Synchronous Signal
1 Source Is Asynchronous Signal
0 EVT1SRCSEL DCAEVT1 Source Signal Select
0 Source Is DCAEVT1 Signal
1 Source Is DCEVTFILT Signal
1818
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated