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ePWM Registers

Table 34-47. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued)

Bits Name Value Description

3-2 INTCNT ePWM Interrupt Event (EPWMx_INT) Counter Register

These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are

automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL[INT] =

0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting events when it reaches

the period value ETPS[INTCNT] = ETPS[INTPRD].

0 No events have occurred.

1h 1 event has occurred.

2h 2 events have occurred.

3h 3 events have occurred.

1-0 INTPRD ePWM Interrupt (EPWMx_INT) Period Select

These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt

is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt

status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will be generated until

the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another

is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be

cleared.

Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is

enabled and the status flag is clear.

Writing a INTPRD value that is less than the current counter value will result in an undefined state.

If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written,

the counter is incremented.

0 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.

1h Generate an interrupt on the first event INTCNT = 01 (first event)

2h Generate interrupt on ETPS[INTCNT] = 1,0 (second event)

3h Generate interrupt on ETPS[INTCNT] = 1,1 (third event)

1813

SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module

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