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ePWM Registers

Table 34-45. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued)

Bits Name Value Description

2-0 INTSEL ePWM Interrupt (EPWMx_INT) Selection Options

0 Reserved

1h Enable event time-base counter equal to zero. (TBCTR = 0x0000)

2h Enable event time-base counter equal to period (TBCTR = TBPRD)

3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD).

This mode is useful in up-down count mode.

4h Enable event time-base counter equal to CMPA when the timer is incrementing.

5h Enable event time-base counter equal to CMPA when the timer is decrementing.

6h Enable event: time-base counter equal to CMPB when the timer is incrementing.

7h Enable event: time-base counter equal to CMPB when the timer is decrementing.

34.4.6.2 Event-Trigger Flag Register (ETFLG)

Figure 34-86. Event-Trigger Flag Register (ETFLG) [offset = 36h]

15 8

Reserved

R-0

7 4 3 2 1 0

Reserved SOCB SOCA Reserved INT

R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34-46. Event-Trigger Flag Register (ETFLG) Field Descriptions

Bits Name Value Description

15-4 Reserved 0 Reserved

3 SOCB Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag

0 Indicates no EPWMxSOCB event occurred

1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB

output will continue to be generated even if the flag bit is set.

2 SOCA Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag

Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit is

set.

0 Indicates no event occurred

1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA

output will continue to be generated even if the flag bit is set.

1 Reserved 0 Reserved

0 INT Latched ePWM Interrupt (EPWMx_INT) Status Flag

0 Indicates no event occurred

1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be

generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit

is still set. If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared.

Refer to Figure 34-41.

1811

SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module

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