Datasheet
ePWM Registers
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34.4.6 Event-Trigger Submodule Registers
34.4.6.1 Event-Trigger Selection Register (ETSEL)
Figure 34-85. Event-Trigger Selection Register (ETSEL) [offset = 32h]
15 14 12 11 10 8
SOCBEN SOCBSEL SOCAEN SOCASEL
R/W-0 R/W-0 R/W-0 R/W-0
7 4 3 2 0
Reserved INTEN INTSEL
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-45. Event-Trigger Selection Register (ETSEL) Field Descriptions
Bits Name Value Description
15 SOCBEN Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
0 Disable EPWMxSOCB.
1 Enable EPWMxSOCB pulse.
14-12 SOCBSEL EPWMxSOCB Selection Options
These bits determine when a EPWMxSOCB pulse will be generated.
0 Enable DCBEVT1.soc event
1h Enable event time-base counter equal to zero. (TBCTR = 0x0000)
2h Enable event time-base counter equal to period (TBCTR = TBPRD)
3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD).
This mode is useful in up-down count mode.
4h Enable event time-base counter equal to CMPA when the timer is incrementing.
5h Enable event time-base counter equal to CMPA when the timer is decrementing.
6h Enable event: time-base counter equal to CMPB when the timer is incrementing.
7h Enable event: time-base counter equal to CMPB when the timer is decrementing.
11 SOCAEN Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
0 Disable EPWMxSOCA.
1 Enable EPWMxSOCA pulse.
10-8 SOCASEL EPWMxSOCA Selection Options
These bits determine when a EPWMxSOCA pulse will be generated.
0 Enable DCAEVT1.soc event
1h Enable event time-base counter equal to zero. (TBCTR = 0x0000)
2h Enable event time-base counter equal to period (TBCTR = TBPRD)
3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD).
This mode is useful in up-down count mode.
4h Enable event time-base counter equal to CMPA when the timer is incrementing.
5h Enable event time-base counter equal to CMPA when the timer is decrementing.
6h Enable event: time-base counter equal to CMPB when the timer is incrementing.
7h Enable event: time-base counter equal to CMPB when the timer is decrementing.
7-4 Reserved 0 Reserved
3 INTEN Enable ePWM Interrupt (EPWMx_INT) Generation
0 Disable EPWMx_INT generation
1 Enable EPWMx_INT generation
1810
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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