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ePWM Registers

34.4.5.7 Trip-Zone Force Register (TZFRC)

Figure 34-84. Trip-Zone Force Register (TZFRC) [offset = 30h]

15 8

Reserved

R-0

7 6 5 4 3 2 1 0

Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 OST CBC Reserved

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R- 0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34-44. Trip-Zone Force Register (TZFRC) Field Descriptions

Bits Name Value Description

15-7 Reserved 0 Reserved

6 DCBEVT2 Force Flag for Digital Compare Output B Event 2

0 Writing 0 has no effect. This bit always reads back 0.

1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit.

5 DCBEVT1 Force Flag for Digital Compare Output B Event 1

0 Writing 0 has no effect. This bit always reads back 0.

1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit.

4 DCAEVT2 Force Flag for Digital Compare Output A Event 2

0 Writing 0 has no effect. This bit always reads back 0.

1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit.

3 DCAEVT1 Force Flag for Digital Compare Output A Event 1

0 Writing 0 has no effect. This bit always reads back 0

1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit.

2 OST Force a One-Shot Trip Event via Software

0 Writing of 0 is ignored. Always reads back a 0.

1 Forces a one-shot trip event and sets the TZFLG[OST] bit.

1 CBC Force a Cycle-by-Cycle Trip Event via Software

0 Writing of 0 is ignored. Always reads back a 0.

1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.

0 Reserved 0 Reserved

1809

SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module

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