Datasheet

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34.4.5.6 Trip-Zone Flag Register (TZFLG)
Figure 34-83. Trip-Zone Flag Register (TZFLG) [offset = 2Ch]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved DCBEVT2 DCBEVT1 DCAEVT2 DCAEVT1 OST CBC INT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-43. Trip-Zone Flag Register (TZFLG) Field Descriptions
Bit Field Value Description
15-7 Reserved 0 Reserved
6 DCBEVT2 Latched Status Flag for Digital Compare Output B Event 2
0 Indicates no trip event has occurred on DCBEVT2
1 Indicates a trip event has occurred for the event defined for DCBEVT2
5 DCBEVT1 Latched Status Flag for Digital Compare Output B Event 1
0 Indicates no trip event has occurred on DCBEVT1
1 Indicates a trip event has occurred for the event defined for DCBEVT1
4 DCAEVT2 Latched Status Flag for Digital Compare Output A Event 2
0 Indicates no trip event has occurred on DCAEVT2
1 Indicates a trip event has occurred for the event defined for DCAEVT2
3 DCAEVT1 Latched Status Flag for Digital Compare Output A Event 1
0 Indicates no trip event has occurred on DCAEVT1
1 Indicates a trip event has occurred for the event defined for DCAEVT1
2 OST Latched Status Flag for A One-Shot Trip Event
0 No one-shot trip event has occurred.
1 Indicates a trip event has occurred on a pin selected as a one-shot trip source.
This bit is cleared by writing the appropriate value to the TZCLR register.
1 CBC Latched Status Flag for Cycle-By-Cycle Trip Event
0 No cycle-by-cycle trip event has occurred.
1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The
TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip
event is still present when the CBC bit is cleared, then CBC will be immediately set again. The
specified condition on the signal is automatically cleared when the ePWM time-base counter
reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the
signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is
cleared.
This bit is cleared by writing the appropriate value to the TZCLR register.
0 INT Latched Trip Interrupt Status Flag
0 Indicates no interrupt has been generated.
1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition.
No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt
flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated.
Clearing all flag bits will prevent further interrupts.
This bit is cleared by writing the appropriate value to the TZCLR register.
1808
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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