Datasheet

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34.4.1.3 Time-Base Phase Register (TBPHS)
Figure 34-65. Time-Base Phase Register (TBPHS) [offset = 06h]
15 0
TBPHS
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-25. Time-Base Phase Register (TBPHS) Field Descriptions
Bits Name Description
15-0 TBPHS These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying
the synchronization input signal.
• If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not loaded
with the phase.
• If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS)
when a synchronization event occurs. The synchronization event can be initiated by the input
synchronization signal (EPWMxSYNCI) or by a software forced synchronization.
34.4.1.4 Time-Base Period Register (TBPRD)
Figure 34-66. Time-Base Period Register (TBPRD) [offset = 0Ah]
15 0
TBPRD
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-26. Time-Base Period Register (TBPRD) Field Descriptions
Bits Name Description
15-0 TBPRD These bits determine the period of the time-base counter. This sets the PWM frequency.
Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
• If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the
shadow register. In this case, the active register will be loaded from the shadow register when the time-
base counter equals zero.
• If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active
register, that is the register actively controlling the hardware.
• The active and shadow registers share the same memory map address.
34.4.1.5 Time-Base Counter Register (TBCTR)
Figure 34-67. Time-Base Counter Register (TBCTR) [offset = 08h]
15 0
TBCTR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-27. Time-Base Counter Register (TBCTR) Field Descriptions
Bits Name Description
15-0 TBCTR Reading these bits gives the current time-base counter value.
Writing to these bits sets the current time-base counter value. The update happens as soon as the write
occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed.
1791
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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