Datasheet

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Table 34-22. ePWM Module Control and Status Register Set Grouped by Submodule (continued)
Address Offset Name Description Section
6Ch DCFOFFSETCNT Digital Compare Filter Offset Counter Register Section 34.4.8.8
6Eh DCFWINDOW Digital Compare Filter Window Register Section 34.4.8.7
70h DCFWINDOWCNT Digital Compare Filter Window Counter Register Section 34.4.8.10
72h DCCAP Digital Compare Counter Capture Register Section 34.4.8.9
34.4.1 Time-Base Submodule Registers
34.4.1.1 Time-Base Status Register (TBSTS)
Figure 34-63. Time-Base Status Register (TBSTS) [offset = 02h]
15 8
Reserved
R-0
7 3 2 1 0
Reserved CTRMAX SYNCI CTRDIR
R-0 R/W1C-0 R/W1C-0 R-1
LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset
Table 34-23. Time-Base Status Register (TBSTS) Field Descriptions
Bit Field Value Description
15-3 Reserved 0 Reserved
2 CTRMAX Time-Base Counter Max Latched Status Bit
0 Read: Indicates the time-base counter never reached its maximum value.
Write: No effect.
1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF.
Write: Clears the latched event.
1 SYNCI Input Synchronization Latched Status Bit
0 Read: Indicates no external synchronization event has occurred.
Write: No effect.
1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI).
Write: Clears the latched event.
0 CTRDIR Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no
meaning. To make this bit meaningful, you must first set the appropriate mode via
TBCTL[CTRMODE].
0 Time-Base Counter is currently counting down.
1 Time-Base Counter is currently counting up.
1788
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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