Datasheet

Sync DCBEVT2.force
1
0
TBCLK
DCBEVT2
1
0
TZFRC[DCBEVT2]
Latch
set
clear
TZCLR[DCBEVT2] TZFLG[DCBEVT2]
TZEINT[DCBEVT2]
DCBEVT2.inter
async
DCEVTFILT
DCBCTL[EVT2FRCSYNCSEL]
DCBCTL[EVT2SRCSEL]
Sync DCBEVT1.force
1
0
TBCLK
DCBEVT1
1
0
TZFRC[DCBEVT1]
DCBEVT1.soc
DCBCTL[EVT1SOCE]
Latch
set
clear
TZCLR[DCBEVT1] TZFLG[DCBEVT1]
TZEINT[DCBEVT1]
DCBEVT1.inter
DCBEVT1.sync
DCBCTL[EVT1SYNCE]
async
DCEVTFILT
DCBCTL[EVT1FRCSYNCSEL]
DCBCTL[EVT1SRCSEL]
www.ti.com ePWM Submodules
Figure 34-47 and Figure 34-48 show how the DCBEVT1, DCBEVT2, or DCEVTFILT signals are
processed to generate the digital compare B event force, interrupt, soc and sync signals.
Figure 34-47. DCBEVT1 Event Triggering
Figure 34-48. DCBEVT2 Event Triggering
1769
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated