Datasheet

Latch
Generate
SOC
Pulse
When
Input = 1
2-bit
Counter
Set
Clear
ClearCNT
IncCNT
ETPS[SOCACNT]
ETPS[SOCAPRD]
ETCLR[SOCA]
SOCA
ETFRC[SOCA]
ETSEL[SOCA]
000
001
010
011
100
101
111
101
DCAEVT1.soc
[A]
ETFLG[SOCA]
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
ETSEL[SOCASEL]
CTR=Zero
CTR=PRD
Latch
Generate
Interrupt
Pulse
When
Input = 1
2-bit
Counter
Set
Clear
1
0
0
ClearCNT
IncCNT
ETPS[INTCNT]
ETPS[INTPRD]
ETCLR[INT]
EPWMxINT
ETFRC[INT]
ETSEL[INT]
000
001
010
011
100
101
111
101
0
ETFLG[INT]
CTR=Zero
CTR=PRD
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
ETSEL[INTSEL]
ePWM Submodules www.ti.com
Figure 34-41. Event-Trigger Interrupt Generator
Figure 34-42 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The
ETPS[SOCACNT] counter and ETPS[SOCAPRD] period values behave similarly to the interrupt generator
except that the pulses are continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a
pulse is generated, but it does not stop further pulse generation. The enable/disable bit ETSEL[SOCAEN]
stops pulse generation, but input events can still be counted until the period value is reached as with the
interrupt generation logic. The event that will trigger an SOCA and SOCB pulse can be configured
separately in the ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same
events that can be specified for the interrupt generation logic with the addition of the DCAEVT1.soc and
DCBEVT1.soc event signals from the digital compare (DC) submodule.
Figure 34-42. Event-Trigger SOCA Pulse Generator
A The DCAEVT1.soc signals are signals generated by the Digital compare (DC) submodule, described in Section 34.2.9
1764
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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