Datasheet

VIM
Event Trigger
Module Logic
CTR=Zero
CTR=PRD
CTR=CMPA
EPWMxINTn
CTR=CMPB
CTR_dir
Direction
qualifier
CTRU=CMPA
ETSEL reg
EPWMxSOCA
/n
/n
/n
EPWMxSOCB
ADC
clear
count
count
clear
count
clear
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
ETPS reg
ETFLG reg
ETCLR reg
ETFRC reg
CTR=Zero or PRD
DCAEVT1.soc
DCBEVT1.soc
From Digital Compare
(DC) Submodule
ePWM Submodules www.ti.com
The event-trigger submodule monitors various event conditions (the left side inputs to event-trigger
submodule shown in Figure 34-40) and can be configured to prescale these events before issuing an
Interrupt request or an ADC start of conversion. The event-trigger prescaling logic can issue Interrupt
requests and ADC start of conversion at:
• Every event
• Every second event
• Every third event
Figure 34-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
The key registers used to configure the event-trigger submodule are listed in Table 34-20.
Table 34-20. Event-Trigger Submodule Registers
Register Name Address Offset Shadowed Description
ETSEL 32h No Event-trigger Selection Register
ETFLG 36h No Event-trigger Flag Register
ETPS 34h No Event-trigger Prescale Register
ETFRC 3Ah No Event-trigger Force Register
ETCLR 38h No Event-trigger Clear Register
• ETSEL—This selects which of the possible events will trigger an interrupt or start an ADC conversion
• ETPS—This programs the event prescaling options mentioned above.
• ETFLG—These are flag bits indicating status of the selected and prescaled events.
• ETCLR—These bits allow you to clear the flag bits in the ETFLG register via software.
• ETFRC—These bits allow software forcing of an event. Useful for debugging or s/w intervention.
A more detailed look at how the various register bits interact with the Interrupt and ADC start of
conversion logic are shown in Figure 34-41, Figure 34-42, and Figure 34-43.
1762
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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