Datasheet

Clear
Latch
Set
TZCLR[CBC]
CBCForce
OutputEvent
TZEINT[CBC]
TZFLG[CBC]
Clear
Latch
Set
TZCLR[OST]
OSTForce
OutputEvent
TZEINT[OST]
TZFLG[OST]
Clear
Latch
Set
TZCLR[DCAEVT1]
DCAEVT1.inter
TZEINT[DCAEVT1]
TZFLG[DCAEVT1]
Clear
Latch
Set
TZCLR[DCAEVT2]
DCAEVT2.inter
TZEINT[DCAEVT2]
TZFLG[DCAEVT2]
Clear
Latch
Set
TZCLR[DCBEVT1]
DCBEVT1.inter
TZEINT[DCBEVT1]
TZFLG[DCBEVT1]
Clear
Latch
Set
TZCLR[DCBEVT2]
DCBEVT2.inter
TZEINT[DCBEVT2]
TZFLG[DCBEVT2]
Generate
Interrupt
Pulse
When
Input=1
Clear
Latch
Set
TZFLG[INT]
TZCLR[INT]
EPWMxTZINT(PIE)
www.ti.com ePWM Submodules
Figure 34-37. Trip-Zone Submodule Interrupt Logic
1759
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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