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ePWM Submodules

34.2.7.2 Controlling and Monitoring the Trip-Zone Submodule

The trip-zone submodule operation is controlled and monitored through the following registers:

Table 34-18. Trip-Zone Submodule Registers

(1)

TZDCSEL 26h No Trip-zone Digital Compare Select Register

(2)

TZSEL 24h No Trip-Zone Select Register

TZEINT 2Ah No Trip-Zone Enable Interrupt Register

TZCTL 28h No Trip-Zone Control Register

TZCLR 2Eh No Trip-Zone Clear Register

TZFLG 2Ch No Trip-Zone Flag Register

TZFRC 30h No Trip-Zone Force Register

(1)

All trip-zone registers are writable only in privileged mode.

(2)

This register is discussed in more detail in Section 34.2.9 .

34.2.7.3 Operational Highlights for the Trip-Zone Submodule

The following sections describe the operational highlights and configuration options for the trip-zone

submodule.

The trip-zone signals TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals. When

one of these signals goes low, or when a DCAEVT1/2 or DCBEVT1/2 force happens based on the

TZDCSEL register event selection, it indicates that a trip event has occurred. Each ePWM module can be

individually configured to ignore or use each of the trip-zone signals or DC events. Which trip-zone signals

or DC events are used by a particular ePWM module is determined by the TZSEL register for that specific

ePWM module. The trip-zone signals may or may not be synchronized to the system clock (VCLK3) and

digitally filtered within the GPIO MUX block. A minimum of 3 × TBCLK low pulse width on TZn inputs is

sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip

condition may not be latched. The asynchronous trip makes sure that if clocks are missing for any reason,

the outputs can still be tripped by a valid event present on TZn inputs. The GPIOs or peripherals must be

appropriately configured. For more information, see the IOMM chapter of the device technical reference

manual.

Each TZn input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for

an ePWM module. DCAEVT1 and DCBEVT1 events can be configured to directly trip an ePWM module or

provide a one-shot trip event to the module. Likewise, DCAVET2 and DCBEVT2 events can also be

configured to directly trip an ePWM module or provide a cycle-by-cycle trip event to the module. This

configuration is determined by the TZSEL[DCAEVT1/2], TZSEL[DCBEVT1/2], TZSEL[CBCn], and

TZSEL[OSHTn] control bits (where n corresponds to the trip input) respectively.

• Cycle-by-Cycle (CBC):

When a cycle-by-cycle trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits

is carried out immediately on the EPWMxA and/or EPWMxB output. Table 34-19 lists the possible

actions. In addition, the cycle-by-cycle trip event flag (TZFLG[CBC]) is set and a EPWMx_TZINT

interrupt is generated if it is enabled in the TZEINT register and VIM peripheral.

If the CBC interrupt is enabled via the TZEINT register, and DCAEVT2 or DCBEVT2 are selected as

CBC trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT2 or DCBEVT2

interrupts in the TZEINT register, as the DC events trigger interrupts through the CBC mechanism.

The specified condition on the inputs is automatically cleared when the ePWM time-base counter

reaches zero (TBCTR = 0x0000) if the trip event is no longer present. Therefore, in this mode, the trip

event is cleared or reset every PWM cycle. The TZFLG[CBC] flag bit will remain set until it is manually

cleared by writing to the TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the

TZFLG[CBC] bit is cleared, then it will again be immediately set.

1755

SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module

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