Datasheet

SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Data Valid
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
5
4
7
6
198
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Figure 7-20. SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 7-21. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)