Datasheet

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The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × T
TBCLK
RED = DBRED × T
TBCLK
Where T
TBCLK
is the period of TBCLK, the prescaled version of VCLK3.
For convenience, delay values for various TBCLK options are shown in Table 34-15.
Table 34-15. Dead-Band Delay Values in μS as a Function of DBFED and DBRED
Dead-Band Value Dead-Band Delay in μS
DBFED, DBRED TBCLK = VCLK3/1 TBCLK = VCLK3 /2 TBCLK = VCLK3/4
1 0.02 μS 0.03 μS 0.07 μS
5 0.08 μS 0.17 μS 0.33 μS
10 0.17 μS 0.33 μS 0.67 μS
100 1.67 μS 3.33 μS 6.67 μS
200 3.33 μS 6.67 μS 13.33 μS
400 6.67 μS 13.33 μS 26.67 μS
500 8.33 μS 16.67 μS 33.33 μS
600 10.00 μS 20.00 μS 40.00 μS
700 11.67 μS 23.33 μS 46.67 μS
800 13.33 μS 26.67 μS 53.33 μS
900 15.00 μS 30.00 μS 60.00 μS
1000 16.67 μS 33.33 μS 66.67 μS
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay
becomes:
FED = DBFED × T
TBCLK
/2
RED = DBRED × T
TBCLK
/2
1749
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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