Datasheet
197
RM57L843
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SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t
c(VCLK)
= interface clock cycle time = 1 / f
(VCLK)
(3) For rise and fall timings, see the Table 5-4.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(VCLK)
≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)
(1)(2)(3)
NO. Parameter MIN MAX Unit
1 t
c(SPC)M
Cycle time, SPICLK
(4)
40 256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3 ns
t
w(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3 ns
t
w(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3
4
(5)
t
v(SIMO-SPCH)M
Valid time, SPICLK high after
SPISIMO data valid (clock polarity =
0)
0.5t
c(SPC)M
– 6 ns
t
v(SIMO-SPCL)M
Valid time, SPICLK low after
SPISIMO data valid (clock polarity =
1)
0.5t
c(SPC)M
– 6
5
(5)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5t
c(SPC)M
– t
r(SPC)
– 4 ns
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5t
c(SPC)M
– t
f(SPC)
– 4
6
(5)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
t
r(SPC)
+ 2.2 ns
t
su(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
t
f(SPC)
+ 2.2
7
(5)
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
10 ns
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
10
8
(6)
t
C2TDELAY
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD = 0 0.5*t
c(SPC)M
+
(C2TDELAY+2) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
– 7
0.5*t
c(SPC)M
+
(C2TDELAY+2) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
+ 5.5
ns
CSHOLD = 1 0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
– 7
0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
+ 5.5
Setup time CS
active until SPICLK
low (clock polarity =
1)
CSHOLD = 0 0.5*t
c(SPC)M
+
(C2TDELAY+2) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
– 7
0.5*t
c(SPC)M
+
(C2TDELAY+2) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
+ 5.5
ns
CSHOLD = 1 0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
– 7
0.5*t
c(SPC)M
+
(C2TDELAY+3) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
+ 5.5
9
(6)
t
T2CDELAY
Hold time SPICLK low until CS
inactive (clock polarity = 0)
T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
-
7
T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
+
11
ns
Hold time SPICLK high until CS
inactive (clock polarity = 1)
T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
-
7
T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
+
11
ns
10 t
SPIENA
SPIENAn Sample Point (C2TDELAY+1)* t
c(VCLK)
-
t
f(SPICS)
– 29
(C2TDELAY+1)*t
c(VCLK)
ns
11 t
SPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*t
c(VCLK)
ns