Datasheet

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1961

TBCTR

EPWMxA

EPWMxB

TBPRD

value

CBCB

ePWM Submodules

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Figure 34-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on

EPWMxA and EPWMxB — Active Low

A PWM period = 2 x TBPRD × T

TBCLK

B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).

C Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).

D Outputs EPWMxA and EPWMxB can drive independent power switches

Example 34-4 contains a code sample showing initialization and run time for the waveforms in Figure 34-

24.

Example 34-4. Code Sample for Figure 34-24

// Initialization Time

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm1Regs.TBPRD = 600; // Period = 2´600 TBCLK counts

EPwm1Regs.CMPA.half.CMPA = 400; // Compare A = 400 TBCLK counts

EPwm1Regs.CMPB = 500; // Compare B = 500 TBCLK counts

EPwm1Regs.TBPHS = 0; // Set Phase register to zero

EPwm1Regs.TBCTR = 0; // clear TB counter

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetric

xEPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

xEPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = VCLK3

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;

EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;

// Run Time

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A

EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B

1742

Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014

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