Datasheet

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Table 34-4. Key Time-Base Signals (continued)
Signal Description
CTR = CMPB Time-base counter equal to active counter-compare B register (TBCTR = CMPB).
This event is generated by the counter-compare submodule and used by the synchronization out logic
CTR_dir Time-base counter direction.
Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
increasing and low when it is decreasing.
CTR_max Time-base counter equal max value. (TBCTR = 0xFFFF)
Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a status
bit
TBCLK Time-base clock.
This is a prescaled version of the system clock (VCLK3) and is used by all submodules within the ePWM. This
clock determines the rate at which time-base counter increments or decrements.
34.2.2.3 Calculating PWM Period and Frequency
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the
time-base counter. Figure 34-5 shows the period (T
pwm
) and frequency (F
pwm
) relationships for the up-
count, down-count, and up-down-count time-base counter modes when the period is set to 4 (TBPRD =
4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled
version of the system clock (VCLK3).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
• Up-Down-Count Mode:
In up-down-count mode, the time-base counter starts from zero and increments until the period
(TBPRD) value is reached. When the period value is reached, the time-base counter then decrements
until it reaches zero. At this point the counter repeats the pattern and begins to increment.
• Up-Count Mode:
In this mode, the time-base counter starts from zero and increments until it reaches the value in the
period register (TBPRD). When the period value is reached, the time-base counter resets to zero and
begins to increment once again.
• Down-Count Mode:
In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until
it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins
to decrement once again.
34.2.2.3.1 Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register
The active register controls the hardware and is responsible for actions that the hardware causes or
invokes.
• Shadow Register
The shadow register buffers or provides a temporary holding location for the active register. It has no
direct effect on any control hardware. At a strategic point in time the shadow register's content is
transferred to the active register. This prevents corruption or spurious operation due to the register
being asynchronously modified by software.
1721
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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