Datasheet

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1941

Digital Compare

Signals

Counter Compare

Signals

T ime Base

Signals

Dead

Band

(DB)

Counter

Compare

(CC)

Action

Qualifier

(AQ)

EPWMxA

EPWMxB

CTR = CMPB

CTR = 0

EPWMxINT

EPWMxSOCA

EPWMxSOCB

EPWMxA

EPWMxB

nTZ1 to nTZ3

CTR = CMPA

T ime-Base

(TB)

CTR = PRD

CTR = 0

CTR_Dir

EPWMxSYNCI

EPWMxSYNCO

EPWMxTZINT

PWM-

chopper

(PC)

Event

Trigger

and

Interrupt

(ET)

Trip

Zone

(TZ)

GPIO

MUX

ADC

VIM

Digital

Compare

(DC)

CPU Debug Mode

OSCFAIL or PLL SLip

Combination of EQEP1ERR

and EQEP2ERR

Digital Compare

Signals

Digital Compare

Signals

VIM

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ePWM Submodules

34.2.2 Time-Base (TB) Submodule

Each ePWM module has its own time-base submodule that determines all of the event timing for the

ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work

together as a single system. Figure 34-3 illustrates the time-base module's place within the ePWM.

Figure 34-3. Time-Base Submodule Block Diagram

34.2.2.1 Purpose of the Time-Base Submodule

You can configure the time-base submodule for the following:

• Specify the ePWM time-base counter (TBCTR) frequency or period to control how often events occur.

• Manage time-base synchronization with other ePWM modules.

• Maintain a phase relationship with other ePWM modules.

• Set the time-base counter to count-up, count-down, or count-up-and-down mode.

• Generate the following events:

– CTR = PRD: Time-base counter equal to the specified period (TBCTR = TBPRD).

– CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000).

• Configure the rate of the time-base clock; a prescaled version of the device peripheral clock domain

(VCLK3). This allows the time-base counter to increment/decrement at a slower rate.

34.2.2.2 Controlling and Monitoring the Time-Base Submodule

Table 34-3 shows the registers used to control and monitor the time-base submodule.