Datasheet

EPWMxINT
EPWMxTZINT
EPWMxSOCA
EPWMxSOCB
EPWMxSYNCI
EPWMxSYNCO
Time-base (TB) module
Counter-compare (CC) module
Action-qualifier (AQ) module
Dead-band (DB) module
PWM-chopper (PC) module
Event-trigger (ET) module
Trip-zone (TZ) module
Peripheral bus
ePWM module
nTZ1 to TZ3
EPWMxA
EPWMxB
VIM
ADC
GPIO
MUX
Digital Compare (DC) module
EQEP1ERR / EQEP2 ERR
OSCFAIL / PLL Slip
CPU Debug Mode
www.ti.com Introduction
Figure 34-2. Submodules and Signal Connections for an ePWM Module
The main signals used by the ePWM module are:
• PWM output signals (EPWMxA and EPWMxB).
The PWM output signals are made available external to the device through the I/O Multiplexing Module
(IOMM) as described in the IOMM chapter of the device's technical reference manual.
• Trip-zone signals (TZ1 to TZ6).
These input signals alert the ePWM module of fault conditions external to the ePWM module. Each
ePWM module can be configured to either use or ignore any of the trip-zone signals. The TZ1 to TZ3
trip-zone signals can be configured as asynchronous inputs, or double-synchronized using VCLK3, or
double-synchronized and filtered through a 6-VCLK3-cycle counter before connecting to the ePWM
modules. This selection is done by configuring registers in the IOMM. TZ4 is connected to an inverted
eQEP1 error signal (EQEP1ERR), or to an inverted eQEP2 error signal (EQEP2ERR), or an OR-
combination of EQEP1ERR and EQEP2ERR. This selection is also done via the IOMM registers. TZ5
is connected to the system clock fail status. This is asserted whenever an oscillator failure is detected,
or a PLL slip is detected. TZ6 is connected to the debug mode entry indicator output from the CPU.
This allows you to configure a trip action when the CPU halts.
• Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals.
The synchronization signals daisy chain the ePWM modules together. Each module can be configured
to either use or ignore its synchronization input. The clock synchronization input and output signal are
brought out to pins only for ePWM1 (ePWM module #1). The synchronization output for ePWM1
(EPWM1SYNCO) is also connected to the SYNCI of the first enhanced capture module (eCAP1).
• ADC start-of-conversion signals (EPWMxSOCA and EPWMxSOCB).
Each ePWM module has two ADC start of conversion signals. Any ePWM module can trigger a start of
conversion. Which event triggers the start of conversion is configured in the Event-Trigger submodule
of the ePWM.
• Peripheral Bus
The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file.
1715
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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