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33.3.17 eQEP Interrupt Enable Register (QEINT)
Figure 33-37. eQEP Interrupt Enable Register (QEINT) [offset = 30h]
15 12 11 10 9 8
Reserved UTO IEL SEL PCM
R-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
PCR PCO PCU WTO QDC QPE PCE Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33-20. eQEP Interrupt Enable Register (QEINT) Field Descriptions
Bits Name Value Description
15-12 Reserved 0 Always read as 0
11 UTO Unit time out interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
10 IEL Index event latch interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
9 SEL Strobe event latch interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
8 PCM Position-compare match interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
7 PCR Position-compare ready interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
6 PCO Position counter overflow interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
5 PCU Position counter underflow interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
4 WTO Watchdog time out interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
3 QDC Quadrature direction change interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
2 QPE Quadrature phase error interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
1 PCE Position counter error interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
0 Reserved 0 Always read as 0
1706
Enhanced QEP (eQEP) Module SPNU562–May 2014
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