Datasheet

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32.5.12 ECAP Interrupt Clear Register (ECCLR)
Figure 32-25. ECAP Interrupt Clear Register (ECCLR) [offset = 30h]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
CTR_CMP CTR_PRD CTROVF CEVT4 CETV3 CETV2 CETV1 INT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32-13. ECAP Interrupt Clear Register (ECCLR) Field Descriptions
Bits Field Value Description
15-8 Reserved 0 Any writes to these bit(s) must always have a value of 0.
7 CTR_CMP Counter Equal Compare Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CTR_CMP flag condition.
6 CTR_PRD Counter Equal Period Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CTR_PRD flag condition.
5 CTROVF Counter Overflow Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CTROVF flag condition.
4 CEVT4 Capture Event 4 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT4 flag condition.
3 CEVT3 Capture Event 3 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT3 flag condition.
2 CEVT2 Capture Event 2 Status Flag
1 Writing a 0 has no effect. Always reads back a 0.
0 Writing a 1 clears the CEVT2 flag condition.
1 CEVT1 Capture Event 1 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT1 flag condition.
0 INT Global Interrupt Clear Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags
are set to 1.
1673
SPNU562–May 2014 Enhanced Capture (eCAP) Module
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