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32.5.11 ECAP Interrupt Forcing Register (ECFRC)
Figure 32-24. ECAP Interrupt Forcing Register (ECFRC) [offset = 32h]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
CTR_CMP CTR_PRD CTROVF CEVT4 CETV3 CETV2 CETV1 reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32-12. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
Bits Field Value Description
15-8 Reserved 0 Any writes to these bit(s) must always have a value of 0.
7 CTR_CMP Force Counter Equal Compare Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR_CMP flag bit.
6 CTR_PRD Force Counter Equal Period Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR_PRD flag bit.
5 CTROVF Force Counter Overflow
0 No effect. Always reads back a 0.
1 Writing a 1 to this bit sets the CTROVF flag bit.
4 CEVT4 Force Capture Event 4
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT4 flag bit.
3 CEVT3 Force Capture Event 3
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT3 flag bit.
2 CEVT2 Force Capture Event 2
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT2 flag bit.
1 CEVT1 Force Capture Event 1
1 No effect. Always reads back a 0.
0 Sets the CEVT1 flag bit.
0 Reserved 0 Any writes to these bit(s) must always have a value of 0.
1672
Enhanced Capture (eCAP) Module SPNU562–May 2014
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