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eCAP Registers

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32.5.7 ECAP Control Register 2 (ECCTL2)

Figure 32-20. ECAP Control Register 2 (ECCTL2) [offset = 2Ah]

15 11 10 9 8

Reserved APWMPOL CAP_APWM SWSYNC

R-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

SYNCO_SEL SYNCI_EN TSCTRSTOP REARM STOP_WRAP CONT_ONESHT

R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32-8. ECAP Control Register 2 (ECCTL2) Field Descriptions

Bits Field Value Description

15-11 Reserved 0 Reserved

10 APWMPOL APWM output polarity select. This is applicable only in APWM operating mode

0 Output is active high (Compare value defines high time)

1 Output is active low (Compare value defines low time)

9 CAP_APWM CAP/APWM operating mode select

0 ECAP module operates in capture mode. This mode forces the following configuration:

• Inhibits TSCTR resets via CTR = PRD event

• Inhibits shadow loads on CAP1 and 2 registers

• Permits user to enable CAP1-4 register load

• CAPx/APWMx pin operates as a capture input

1 ECAP module operates in APWM mode. This mode forces the following configuration:

• Resets TSCTR on CTR = PRD event (period boundary

• Permits shadow loading on CAP1 and 2 registers

• Disables loading of time-stamps into CAP1-4 registers

• CAPx/APWMx pin operates as a APWM output

8 SWSYNC Software-forced Counter (TSCTR) Synchronizing. This provides a convenient software method to

synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via

the CTR = PRD event.

0 Writing a 0 has no effect. Reading always returns a zero

1 Writing a 1 forces a TSCTR shadow load of current ECAP module and any ECAP modules down-

stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a 0.

Note: Selection CTR = PRD is meaningful only in APWM mode; however, you can choose it in CAP

mode if you find doing so useful.

7-6 SYNCO_SEL Sync-Out Select

0 Select sync-in event to be the sync-out signal (pass through)

1h Select CTR = PRD event to be the sync-out signal

2h Disable sync out signal

3h Disable sync out signal

5 SYNCI_EN Counter (TSCTR) Sync-In select mode

0 Disable sync-in option

1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W

force event.

4 TSCTRSTOP Time Stamp (TSCTR) Counter Stop (freeze) Control

0 TSCTR stopped

1 TSCTR free-running

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Enhanced Capture (eCAP) Module SPNU562–May 2014

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