Datasheet

189
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
7.11 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
7.11.1 Features
Both Standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 11-bit baud clock generator
• SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
• Each word transferred can have a unique format
• SPI I/Os not used in the communication can be used as digital input/output signals
Table 7-29. MibSPI Configurations
MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[5:0], MIBSPI5nENA
MibSPI2 MIBSPI2SIMO,MIBSPI2SOMI,MIBSPI2CLK,MIBSPI2nCS[1:0],MIBSPI2nENA
MibSPI4 MIBSPI4SIMO,MIBSPI4SOMI,MIBSPI4CLK,MIBSPI4nCS[5:0],MIBSPI4nENA
7.11.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers for MibSPI1 and 128 buffers for all other MibSPI. Each
entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit
control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer groups
with a variable number of buffers each.
Multibuffered RAM Transfer Groups
MibSPIx/SPIx
MODULES
NO OF CHIP
SELECTS
MIBSPIxnCS[x]
NO. OF RAM
BUFFERS
NO. OF TRANSFER
GROUPS
MibSPI1 6 MIBSPI1nCS[5:0] 256 8
MibSPI2 2 MIBSPI2nCS[1:0] 128 8
MibSPI3 6 MIBSPI3nCS[5:0] 128 8
MibSPI4 6 MIBSPI4nCS[5:0] 128 8
MibSPI5 6 MIBSPI5nCS[5:0] 128 8
7.11.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used
by each transfer group.