Datasheet

CEVT1 CEVT2 CEVT3 CEVT4 CEVT1

CAPx pin

0 1 2 3 0 1

XX t

Capture registers [1−4]

All capture values valid

(can be read) at this time

00000000

FFFFFFFF

CTR[0−31]

MOD4

CTR

CAP1

CAP2

CAP3

CAP4

Polarity selection

Application of the ECAP Module

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32.3.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger

Figure 32-9 shows an example of continuous capture operation (Mod4 counter wraps around). In this

figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this

gives period (and frequency) information.

On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the

next state. When the TSCTR reaches FFFFFFFF (maximum value), it wraps around to 00000000 (not

shown in Figure 32-9), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if

enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured

Time-stamps are valid at the point indicated by the diagram, after the 4th event, hence event CEVT4 can

conveniently be used to trigger an interrupt and the CPU can read data from the CAPx registers.

Figure 32-9. Capture Sequence for Absolute Time-stamp and Rising Edge Detect

1654

Enhanced Capture (eCAP) Module SPNU562–May 2014

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