Datasheet

EMAC Module Registers

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31.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)

The transmit channel 0-7 completion pointer register (TX nCP) is shown in Figure 31-86 and described in

Table 31-87.

Figure 31-86. Transmit Channel n Completion Pointer Register (TXnCP) (offset = 640h-65Ch)

31 0

TXnCP

R/W-x

LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset

Table 31-87. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions

Bit Field Description

31-0 TXnCP Transmit channel n completion pointer register is written by the host with the buffer descriptor address for the last

buffer processed by the host during interrupt processing. The EMAC uses the value written to determine if the

interrupt should be deasserted.

31.5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)

The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 31-87 and described in

Table 31-88.

Figure 31-87. Receive Channel n Completion Pointer Register (RXnCP) (offset = 660h-67Ch)

31 0

RXnCP

R/W-x

LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset

Table 31-88. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions

Bit Field Description

31-0 RXnCP Receive channel n completion pointer register is written by the host with the buffer descriptor address for the last

buffer processed by the host during interrupt processing. The EMAC uses the value written to determine if the

interrupt should be deasserted.

1634

EMAC/MDIO Module SPNU562–May 2014

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