Datasheet

www.ti.com EMAC Module Registers
31.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)
The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 31-63 and described in
Table 31-64.
Figure 31-63. Receive Buffer Offset Register (RXBUFFEROFFSET) (offset = 110h)
31 16
Reserved
R-0
15 0
RXBUFFEROFFSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-64. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-0 RXBUFFEROFFSET 0-FFFFh Receive buffer offset value. These bits are written by the EMAC into each frame SOP
buffer descriptor Buffer Offset field. The frame data begins after the RXBUFFEROFFSET
value of bytes. A value of 0 indicates that there are no unused bytes at the beginning of
the data, and that valid data begins on the first byte of the buffer. A value of Fh (15)
indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid
buffer data starts on byte 16 of the buffer. This value is used for all channels.
31.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 31-64
and described in Table 31-65.
Figure 31-64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
(offset = 114h)
31 16
Reserved
R-0
15 8 7 0
Reserved RXFILTERTHRESH
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXFILTERTHRESH 0-FFh Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
low priority incoming frames. This field should remain 0, if no filtering is desired.
1619
SPNU562–May 2014 EMAC/MDIO Module
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