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EMAC Module Registers

31.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 31-55 and

described in Table 31-56.

Figure 31-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) (offset = B0h)

31 16

Reserved

R-0

15 2 1 0

Reserved HOSTPEND STATPEND

R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 31-56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); raw interrupt read (before mask).

0 STATPEND 0-1 Statistics pending interrupt (STATPEND); raw interrupt read (before mask).

31.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 31-56 and

described in Table 31-57.

Figure 31-56. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) (offset = B4h)

31 16

Reserved

R-0

15 2 1 0

Reserved HOSTPEND STATPEND

R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 31-57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); masked interrupt read.

0 STATPEND 0-1 Statistics pending interrupt (STATPEND); masked interrupt read.

1613

SPNU562–May 2014 EMAC/MDIO Module

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