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EMAC Module Registers

31.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)

The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 31-51 and

described in Table 31-52.

Figure 31-51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) (offset = A0h)

31 16

Reserved

R-0

15 14 13 12 11 10 9 8

RX7THRESH RX6THRESH RX5THRESH RX4THRESH RX3THRESH RX2THRESH RX1THRESH RX0THRESH

PEND PEND PEND PEND PEND PEND PEND PEND

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

RX7PEND RX6PEND RX5PEND RX4PEND RX3PEND RX2PEND RX1PEND RX0PEND

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 31-52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Reserved

15 RX7THRESHPEND 0-1 RX7THRESHPEND raw interrupt read (before mask)

14 RX6THRESHPEND 0-1 RX6THRESHPEND raw interrupt read (before mask)

13 RX5THRESHPEND 0-1 RX5THRESHPEND raw interrupt read (before mask)

12 RX4THRESHPEND 0-1 RX4THRESHPEND raw interrupt read (before mask)

11 RX3THRESHPEND 0-1 RX3THRESHPEND raw interrupt read (before mask)

10 RX2THRESHPEND 0-1 RX2THRESHPEND raw interrupt read (before mask)

9 RX1THRESHPEND 0-1 RX1THRESHPEND raw interrupt read (before mask)

8 RX0THRESHPEND 0-1 RX0THRESHPEND raw interrupt read (before mask)

7 RX7PEND 0-1 RX7PEND raw interrupt read (before mask)

6 RX6PEND 0-1 RX6PEND raw interrupt read (before mask)

5 RX5PEND 0-1 RX5PEND raw interrupt read (before mask)

4 RX4PEND 0-1 RX4PEND raw interrupt read (before mask)

3 RX3PEND 0-1 RX3PEND raw interrupt read (before mask)

2 RX2PEND 0-1 RX2PEND raw interrupt read (before mask)

1 RX1PEND 0-1 RX1PEND raw interrupt read (before mask)

0 RX0PEND 0-1 RX0PEND raw interrupt read (before mask)

1609

SPNU562–May 2014 EMAC/MDIO Module

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