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31.5.5 Receive Control Register (RXCONTROL)
The receive control register (RXCONTROL) is shown in Figure 31-43 and described in Table 31-44.
Figure 31-43. Receive Control Register (RXCONTROL) (offset = 14h)
31 16
Reserved
R-0
15 1 0
Reserved RXEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-44. Receive Control Register (RXCONTROL) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 RXEN Receive enable
0 Receive is disabled.
1 Receive is enabled.
31.5.6 Receive Teardown Register (RXTEARDOWN)
The receive teardown register (RXTEARDOWN) is shown in Figure 31-44 and described in Table 31-45.
Figure 31-44. Receive Teardown Register (RXTEARDOWN) (offset = 18h)
31 16
Reserved
R-0
15 3 2 0
Reserved RXTDNCH
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-45. Receive Teardown Register (RXTEARDOWN) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2-0 RXTDNCH Receive teardown channel. The receive channel teardown is commanded by writing the encoded value
of the receive channel to be torn down. The teardown register is read as 0.
0 Teardown receive channel 0
1h Teardown receive channel 1
2h Teardown receive channel 2
3h Teardown receive channel 3
4h Teardown receive channel 4
5h Teardown receive channel 5
6h Teardown receive channel 6
7h Teardown receive channel 7
1602
EMAC/MDIO Module SPNU562–May 2014
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