Datasheet

MDIO Registers

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31.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 31-30 and

described in Table 31-30.

Figure 31-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

(offset = 14h)

31 16

Reserved

R-0

15 2 1 0

Reserved USERPHY1 USERPHY0

R-0 R/W1C-0 R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset

Table 31-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 USERPHY1 MDIO Link change interrupt, masked value. When asserted, the bit indicates that there was an

MDIO link change event (that is, change in the LINK register) corresponding to the PHY address in

USERPHYSEL1 and the corresponding LINKINTENB bit was set. Writing a 1 will clear the event,

writing a 0 has no effect.

0 No MDIO link change event.

1 An MDIO link change event (change in the LINK register) corresponding to the PHY address in

MDIO user PHY select register USERPHYSEL1 and the LINKINTENB bit in USERPHYSEL1 is set

to 1.

0 USERPHY0 MDIO Link change interrupt, masked value. When asserted, the bit indicates that there was an

MDIO link change event (that is, change in the LINK register) corresponding to the PHY address in

USERPHYSEL0 and the corresponding LINKINTENB bit was set. Writing a 1 will clear the event,

writing a 0 has no effect.

0 No MDIO link change event.

1 An MDIO link change event (change in the LINK register) corresponding to the PHY address in

MDIO user PHY select register USERPHYSEL0 and the LINKINTENB bit in USERPHYSEL0 is set

to 1.

1588

EMAC/MDIO Module SPNU562–May 2014

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