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EMAC Control Module Registers

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31.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX)

The EMAC control module receive interrupts per millisecond register (C0RXIMAX) is shown in Figure 31-

23 and described in Table 31-22

Figure 31-23. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX)

(offset = 70h)

31 16

Reserved

R-0

15 6 5 0

Reserved RXIMAX

R-0 R/W-0

LEGEND: R = Read only; R/W = Read/Write; -n = value after reset

Table 31-22. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX)

Bit Field Value Description

31-6 Reserved 0 Reserved

5-0 RXIMAX 2-3Fh RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when

C0RXPACEEN is enabled in INTCONTROL.

The pacing mechanism can be described by the following pseudo-code:

while(1) {

interrupt_count = 0;

/* Count interrupts over a 1ms window */

for(i = 0; i < INTCONTROL[INTPRESCALE]*250; i++) {

interrupt_count += NEW_INTERRUPT_EVENTS();

if(i < INTCONTROL[INTPRESCALE]*pace_counter)

BLOCK_EMAC_INTERRUPTS();

else

ALLOW_EMAC_INTERRUPTS();

}

ALLOW_EMAC_INTERRUPTS();

if(interrupt_count > 2*RXIMAX)

pace_counter = 255;

else if(interrupt_count > 1.5*RXIMAX)

pace_counter = previous_pace_counter*2 + 1;

else if(interrupt_count > 1.0*RXIMAX)

pace_counter = previous_pace_counter + 1;

else if(interrupt_count > 0.5*RXIMAX)

pace_counter = previous_pace_counter - 1;

else if(interrupt_count != 0)

pace_counter = previous_pace_counter/2;

else

pace_counter = 0;

previous_pace_counter = pace_counter;

}

1582

EMAC/MDIO Module SPNU562–May 2014

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