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EMAC Control Module Registers

31.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT)

The EMAC control module receive interrupt status register (C0RXSTAT) is shown in Figure 31-20 and

described in Table 31-19

Figure 31-20. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) (offset = 44h)

31 16

Reserved

R-0

15 8

Reserved

R-0

7 6 5 4 3 2 1 0

RXCH7STAT RXCH6STAT RXCH5STAT RXCH4STAT RXCH3STAT RXCH2STAT RXCH1STAT RXCH0STAT

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 31-19. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT)

Bit Field Value Description

31-8 Reserved 0 Reserved

7 RXCH7STAT Interrupt status for RX Channel 7 masked by the C0RXEN register

0 RX Channel 7 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 7 satisfies conditions to generate a C0RXPULSE interrupt.

6 RXCH6STAT Interrupt status for RX Channel 6 masked by the C0RXEN register

0 RX Channel 6 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 6 satisfies conditions to generate a C0RXPULSE interrupt.

5 RXCH5STAT Interrupt status for RX Channel 5 masked by the C0RXEN register

0 RX Channel 5 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 5 satisfies conditions to generate a C0RXPULSE interrupt.

4 RXCH4STAT Interrupt status for RX Channel 4 masked by the C0RXEN register

0 RX Channel 4 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 4 satisfies conditions to generate a C0RXPULSE interrupt.

3 RXCH3STAT Interrupt status for RX Channel 3 masked by the C0RXEN register

0 RX Channel 3 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 3 satisfies conditions to generate a C0RXPULSE interrupt.

2 RXCH2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register

0 RX Channel 2 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 2 satisfies conditions to generate a C0RXPULSE interrupt.

1 RXCH1STAT Interrupt status for RX Channel 1 masked by the C0RXEN register

0 RX Channel 1 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 1 satisfies conditions to generate a C0RXPULSE interrupt.

0 RXCH0STAT Interrupt status for RX Channel 0 masked by the C0RXEN register

0 RX Channel 0 does not satisfy conditions to generate a C0RXPULSE interrupt.

1 RX Channel 0 satisfies conditions to generate a C0RXPULSE interrupt.

1579

SPNU562–May 2014 EMAC/MDIO Module

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