Datasheet

NHET_LOOP_SYNC EXT_LOOP_SYNC
EXT_LOOP_SYNC
NHET_LOOP_SYNC
N2HET1
N2HET2
179
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
Submit Documentation Feedback
Product Folder Links: RM57L843
Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Table 7-24. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER MIN MAX UNIT
1
Input signal period, PCNT or WCAP for rising edge
to rising edge
(HRP) (LRP) tc
(VCLK2)
+ 2 2
25
(HRP) (LRP) tc
(VCLK2)
- 2 ns
2
Input signal period, PCNT or WCAP for falling edge
to falling edge
(HRP) (LRP) tc
(VCLK2)
+ 2 2
25
(HRP) (LRP) tc
(VCLK2)
- 2 ns
3
Input signal high phase, PCNT or WCAP for rising
edge to falling edge
2 (HRP) tc
(VCLK2)
+ 2 2
25
(HRP) (LRP) tc
(VCLK2)
- 2 ns
4
Input signal low phase, PCNT or WCAP for falling
edge to rising edge
2 (HRP) tc
(VCLK2)
+ 2 2
25
(HRP) (LRP) tc
(VCLK2)
- 2 ns
7.6.4 N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the resynchronization signal from the
master, the slave must synchronize itself again..
Figure 7-15. N2HET1 – N2HET2 Synchronization Hookup