Datasheet

MII_TXCLK
MII_TXD[3−0]
MII_TXEN
MII_COL
MII_CRS
MII_RXCLK
MII_RXD[3−0]
MII_RXDV
MII_RXER
MDIO_CLK
MDIO_D
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz
or
25 MHz
RJ−45
EMACMDIO
Architecture www.ti.com
31.2.3 Signal Descriptions
The microcontrollers support both the MII and the RMII interfaces. Only one of these two interfaces can be
used at a time. A separate control register in the I/O Multiplexing Module (IOMM) allows the application to
indicate the actual interface being used. This is the bit 24 of the PINMMR160 control register. This bit is
set by default and selects the RMII interface. The application can select the MII interface by clearing this
bit. Please refer the I/O Multiplexing Module chapter of the technical reference manual for more details on
the procedure to configure the PINMMR registers.
Each of the EMAC and MDIO signals for the MII and RMII interfaces are multiplexed with other I/O
functions on this microcontroller. Please refer to Section 31.2.4 for information on configuration of the
multiplexing control registers to enable the MII / RMII connections to these I/Os.
31.2.3.1 Media Independent Interface (MII) Connections
Figure 31-2 shows a device with integrated EMAC and MDIO interfaced via a MII connection in a typical
system. The EMAC module does not include a transmit error (MTXER) pin. In the case of transmit error,
CRC inversion is used to negate the validity of the transmitted frame.
The individual EMAC and MDIO signals for the MII interface are summarized in Table 31-1. For more
information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
Figure 31-2. Ethernet Configuration—MII Connections
1528
EMAC/MDIO Module SPNU562–May 2014
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