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I2C Control Registers

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30.6.11 I2C Interrupt Vector Register (I2CIVR)

The I2C interrupt vector register is a 16-bit memory-mapped register used to indicate the occurrence of an

interrupt. Figure 30-24 and Table 30-19 describe this register.

Figure 30-24. I2C Interrupt Vector Register (I2CIVR) [offset = 28h]

15 12 11 8 7 3 2 0

Reserved TESTMD Reserved INTCODE

R-0 R/W-0 R-0 R/WC-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 30-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions

Bit Field Value Description

15-12 Reserved 0 Read returns 0. Writes have no effect.

11-8 TESTMD 0-3h Reserved for internal testing.

7-3 Reserved 0 Read returns 0. Writes have no effect.

2-0 INTCODE 0-3h Interrupt Code Bits

This binary coded interrupt vector indicates which interrupt has occurred. If there is more than

one interrupt pending, reading I2CIVR provides the vector for the highest priority interrupt that is

pending.

Reading the I2CIVR will clear the corresponding flags in I2CSTR for AL, NACK and SCD as

long as those interrupts are enabled. A new interrupt will be generated for each pending source.

Reading I2CIVR will clear the INTCODE for AL, NACK, SCD, AAS, RXRDY and TXRDY.

Reading I2CIVR will not clear the INTCODE for ARDY.

The INTCODE for certains codes can also be cleared by either writing a 1 to the corresponding

interrupt flag bits in I2CSTR, or by reading and writing to the receive or transmit registers. See

Section 30.6.3 for more details.

Users must read (clear) the I2CIVR before doing another start otherwise the I2CIVR could

contain incorrect (old interrupt flag) value.

Table 30-20. Interrupt Codes for INTCODE Bits

Code INTCODE(2-0) Interrupt Occurred

00h 000 none

01h 001 (highest priority) Arbitration lost (AL)

02h 010 No acknowledgement (NACK)

03h 011 Receive access ready (ARDY)

04h 100 Receive data ready (RXRDY)

05h 101 Transmit data ready (TXRDY)

06h 110 Stop condition detection (SCD)

07h 111 (lowest priority) Address as slave (AAS)

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Inter-Integrated Circuit (I2C) Module SPNU562–May 2014

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