Datasheet

www.ti.com I2C Control Registers
30.6.10 I2C Mode Register (I2CMDR)
Figure 30-22 and Table 30-15 describe this register.
Figure 30-22. I2C Mode Register (I2CMDR) [offset = 24h]
15 14 13 12 11 10 9 8
NACKMOD FREE STT Reserved STP MST TRX XA
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 0
RM DLB nIRS STB FDF BC
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-15. I2C Mode Register (I2CMDR) Field Descriptions
Bit Field Value Description
15 NACKMOD No-acknowledge (NACK) mode
This bit is used to send an acknowledge (ACK) or a no-acknowledge (NACK) to the transmitter. This bit
is only applicable when the I2C is in receiver mode. In master receiver mode, when the internal data
counter decrements to zero, the I2C sends a NACK. The master receiver I2C finishes a transfer when it
sends a NACK. The I2C ignores ICCNT when NACKMOD is 1. The NACKMOD bit should be set before
the rising edge of the last data bit if a NACK must be sent, and this bit is cleared once a NACK has
been sent.
0 The I2C sends an ACK to the transmitter during the acknowledge cycle.
1 The I2C sends a NACK to the transmitter during the acknowledge cycle.
14 FREE Free running bit
This bit is used to determine the state of the I2C when a breakpoint is encountered in the high level
language (HLL) debugger.
0 The I2C stops immediately if SCL is low and keeps driving SCL low if the I2C master is a
transmitter/receiver. If SCL is high, I2C waits until SCL becomes low and then stops. If the I2C is a
slave, it will stop when the transmission/reception completes.
1 The I2C runs free.
13 STT Start condition
The start condition bit works with the STP bit (master only mode). The STT and STP bits are configured
to generate different transfer formats (see Table 30-16). The STT and STP bits can be used to
terminate the repeat mode. This bit takes one I2C module clock cycle to set.
0 The STT is reset to 0 by the hardware after the START condition has been generated.
1 STT is set to 1 by the device to generate a START condition. In master mode, setting STT to 1
generates a START condition.
12 Reserved 0 Read returns 0. Writes have no effect.
11 STP Stop condition
1(Master mode only) This bit can be set to a 1 by the CPU to generate a stop condition. It is reset to 0
by the hardware after the stop condition has been generated. The stop condition is generated when
ICCNT passes 0 when the I2C is in non-repeat mode (RM=0). In repeat mode (RM=1), the stop
condition is generated if STP bit is 1. In transmitter mode, I2CTXRDY needs to be 1 (i.e. you have to
set STP bit unless you write data into I2CDXR).
0 STP is reset to 0 by the hardware after the STOP condition has been generated.
1 STP is set to 1 by the device to generate a STOP condition.
10 MST Master/slave mode bit
This bit determines whether the module will operate in master or slave mode; see Table 30-17. This bit
is cleared after generating a STOP condition. The BB bit is cleared first, and MST bit is cleared second.
Before starting the next transaction in master mode, this bit must be confirmed to be cleared.
0 The module is in the slave mode and the clock is received from the master device.
1 The module is in the master mode and it generates the clock. This bit is cleared when the transfer has
completed.
1511
SPNU562–May 2014 Inter-Integrated Circuit (I2C) Module
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