Datasheet

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kFrequencyModuleCloc
dCCLKHI
HighTime
2
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kFrequencyModuleCloc
dCCLKLI
LowTime
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I2C Control Registers www.ti.com
30.6.4 I2C Clock Divider Low Register (I2CCKL)
The I2C clock divider low register is a 16-bit memory mapped register used to divide the master clock
down to obtain the I2C serial clock low time. Figure 30-16 and Table 30-8 describe this register.
Figure 30-16. I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch]
15 0
CLKL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-8. I2C Clock Divider Low Register (I2CCKL) Field Descriptions
Bit Field Description
15-0 CLKL Low time clock division factor
Used to divide down the module clock to create the low time portion of the master clock signal that will appear
on the SCL pin.:
(64)
where d is the value that depends on the I2CPSC (see Section 30.1.3).
This register must be configured while the I2C is still in reset (nIRS = 0).
30.6.5 I2C Clock Control High Register (I2CCKH)
The I2C clock divider high register is a 16-bit memory mapped register used to divide the master clock
down to obtain the I2C serial clock high time. Figure 30-17 and Table 30-9 describe this register.
Figure 30-17. I2C Clock Control High Register (I2CCKH) [offset = 10h]
15 0
CLKH
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-9. I2C Clock Control High Register (I2CCKH) Field Descriptions
Bit Field Description
15-0 CLKH High time clock division factor
Used to divide down the module clock to create the high time portion of the master clock signal that will appear
on the SCL pin:
(65)
where d is the value that depends on the I2CPSC (see Section 30.1.3).
This register must be configured while the I2C is still in reset (nIRS = 0).
1508
Inter-Integrated Circuit (I2C) Module SPNU562–May 2014
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