Datasheet

I2C Control Registers www.ti.com
30.6.2 I2C Interrupt Mask Register (I2CIMR)
The 7-bit memory mapped I2C interrupt mask register is used by the device to enable/disable the
interrupts. Figure 30-14 and Table 30-6 describe this register.
Figure 30-14. I2C Interrupt Mask Register (I2CIMR) [offset = 04h]
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved AASEN SCDEN TXRDYEN RXRDYRN ARDYEN NACKEN ALEN
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-6. I2C Interrupt Mask Register (I2CIMR) Field Descriptions
Bit Field Value Description
15-7 Reserved 0 Read returns 0. Writes have no effect.
6 AASEN Address As Slave Interrupt Enable
0 AASEN interrupt is disabled.
1 AASEN interrupt is enabled.
5 SCDEN Stop Condition Interrupt Enable
0 SCDEN interrupt is disabled.
1 SCDEN interrupt is enabled.
4 TXRDYEN Transmit Data Ready Interrupt Enable
0 TXRDYEN interrupt is disabled.
1 TXRDYEN interrupt is enabled.
3 RXRDYEN Receive Data Ready Interrupt Enable
0 RXRDYEN interrupt is disabled.
1 RXRDYEN interrupt is enabled.
2 ARDYEN Register Access Ready Interrupt Enable
0 ARDYEN interrupt is disabled.
1 ARDYEN interrupt is enabled.
1 NACKEN No Acknowledgement Interrupt Enable
0 NACKEN interrupt is disabled.
1 NACKEN interrupt is enabled.
0 ALEN Arbitration Lost Interrupt Enable
0 ALEN interrupt is disabled.
1 ALEN interrupt is enabled.
1504
Inter-Integrated Circuit (I2C) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated