Datasheet

I2C Control Registers

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30.6 I2C Control Registers

Table 30-3 provides a summary of the control registers. The upper word (upper 16 bits) of the registers all

read as 0s. Writes have no effect on these bits. The base address for the control registers is FFF7 D400h

for I2C1 and FFF7 D500h for I2C2.

Table 30-3. I2C Control Registers

Offset Acronym Register Description Section

00h I2COAR I2C Own Address Manager Section 30.6.1

04h I2CIMR I2C Interrupt Mask Register Section 30.6.2

08h I2CSTR I2C Status Register Section 30.6.3

0Ch I2CCKL I2C Clock Divider Low Register Section 30.6.4

10h I2CCKH I2C Clock Control High Register Section 30.6.5

14h I2CCNT I2C Data Count Register Section 30.6.6

18h I2CDRR I2C Data Receive Register Section 30.6.7

1Ch I2CSAR I2C Slave Address Register Section 30.6.8

20h I2CDXR I2C Data Transmit Register Section 30.6.9

24h I2CMDR I2C Mode Register Section 30.6.10

28h I2CIVR I2C Interrupt Vector Register Section 30.6.11

2Ch I2CEMDR I2C Extended Mode Register Section 30.6.12

30h I2CPSC I2C Prescale Register Section 30.6.13

34h I2CPID1 I2C Peripheral ID Register 1 Section 30.6.14

38h I2CPID2 I2C Peripheral ID Register 2 Section 30.6.15

3Ch I2CDMACR I2C DMA Control Register Section 30.6.16

48h I2CPFNC I2C Pin Function Register Section 30.6.17

4Ch I2CPDIR I2C Pin Direction Register Section 30.6.18

50h I2CDIN I2C Data Input Register Section 30.6.19

54h I2CDOUT I2C Data Output Register Section 30.6.20

58h I2CDSET I2C Data Set Register Section 30.6.21

5Ch I2CDCLR I2C Data Clear Register Section 30.6.22

60h I2CPDR I2C Pin Open Drain Register Section 30.6.23

64h I2CPDIS I2C Pull Disable Register Section 30.6.24

68h I2CPSEL I2C Pull Select Register Section 30.6.25

6Ch I2CSRS I2C Pins Slew Rate Select Register Section 30.6.26

1502

Inter-Integrated Circuit (I2C) Module SPNU562–May 2014

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