Datasheet

V
S1
On-State
Bias Current
Off-State
Leakages
V
S2
V
S24
I
AOSB
I
AIL
I
AIL
R
ext
R
ext
R
ext
P
in
S
mux
R
mux
P
in
S
mux
R
mux
P
in
S
mux
R
mux
S
samp
R
samp
C
samp
C
ext
I
AIL
I
AIL
I
AIL
I
AIL
C
mux
C
ext
C
ext
172
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK1 by a prescale factor defined by the ADCLOCKCR register
bits 4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as
well as the internal impedance of the ADC.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors (for
example, the prescale settings).
Figure 7-10. MibADC Input Equivalent Circuit
Table 7-21. MibADC Timing Specifications
PARAMETER MIN NOM MAX UNIT
t
c(ADCLK)
(1)
Cycle time, MibADC clock 0.033 µs
t
d(SH)
(2)
Delay time, sample and hold time 0.2 µs
12-BIT MODE
t
d(C)
Delay time, conversion time 0.4 µs
t
d(SHC)
(3)
Delay time, total sample/hold and conversion time 0.6 µs
10-BIT MODE
t
d(C)
Delay time, conversion time 0.33 µs
t
d(SHC)
(3)
Delay time, total sample/hold and conversion time 0.53 µs