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SCI Control Registers

Table 29-32. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions (continued)

Bit Field Value Description

18-16 TX SHIFT Transmit shift. These bits define the amount by which the value on TX pin is delayed so that

the value on the RX pin is asynchronous. This feature is not applicable to the start bit.

0 No delay occurs.

1h The value is delayed by 1 SCLK.

2h The value is delayed by 2 SCLK.

3h The value is delayed by 3 SCLK.

4h The value is delayed by 4 SCLK.

5h The value is delayed by 5 SCLK.

6h The value is delayed by 6 SCLK.

7h No delay occurs.

15-12 Reserved 0 Read returns 0. Writes have no effect.

11-8 IODFTENA IODFT enable key. Write access permitted in Privilege mode only.

Ah IODFT is enabled.

All Others IODFT is disabled.

7-2 Reserved 0 Read returns 0. Writes have no effect.

1 LPBENA Module loopback enable. Write access permitted in Privilege mode only.

Note: In analog loopback mode the complete communication path through the I/Os

can be tested, whereas in digital loopback mode the I/O buffers are excluded from

this path.

0 Digital loopback is enabled.

1 Analog loopback is enabled in module I/O DFT mode when IODFTENA = 1010.

0 RXPENA Module analog loopback through receive pin enable. Write access permitted in Privilege

mode only.

This bit defines whether the I/O buffers for the transmit or the receive pin are included in the

communication path (in analog loopback mode)

0 Analog loopback through the transmit pin is enabled.

1 Analog loopback through the receive pin is enabled.

1483

SPNU562–May 2014 Serial Communication Interface (SCI) Module

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