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SCI Control Registers
Table 29-10. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
1 WAKEUP Wakeup flag. This bit is set by the SCI when receiver or transmitter activity has taken the module
out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT[2]) is
set. It is cleared by the following:
Setting of the SW nRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1
For compatibility mode, see the SCI document for more information on lowpower mode.
0 Read: The module will not wake up from power-down mode.
Write: No effect.
1 Read: Wake up from power-down mode.
Write: The bit is cleared to 0.
0 BRKDT SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. A
break condition occurs when the SCIRX pin remains continuously low for at least 10 bits after a
missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to
generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is reset by the
following:
Setting of the SW nRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1
0 Read: No break condition has been detected since the last clear.
Write: No effect.
1 Read: A break condition has been detected.
Write: The bit is cleared to 0.
Table 29-11. SCI Receiver Status Flags
SCI Flag Register Bit Value After SW nRESET
(1)
FE SCIFLR 26 0
OE SCIFLR 25 0
PE SCIFLR 24 0
RXWAKE SCIFLR 12 0
RXRDY SCIFLR 9 0
BRKDT SCIFLR 0 0
(1)
The flags are frozen with their reset value while SW nRESET = 0.
Table 29-12. SCI Transmitter Status Flags
SCI Flag Register Bit Value After SW nRESET
(1)
TX EMPTY SCIFLR 11 1
TXRDY SCIFLR 8 1
(1)
The flags are frozen with their reset value while SW nRESET = 0.
1469
SPNU562May 2014 Serial Communication Interface (SCI) Module
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