Datasheet

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29.4 SCI DMA Interface
DMA requests for receive (RXDMA request) and transmit (TXDMA request) are available for the SCI
module. Refer to the DMA module chapter for DMA module configurations.
29.4.1 Receive DMA Requests
This DMA functionality is enabled/disabled by the CPU using the SET RX DMA/CLR RX DMA bits,
respectively.
The receiver DMA request is set when a frame is received successfully and DMA functionality has been
previously enabled. The RXRDY flag is set when the SCI transfers newly received data from the
SCIRXSHF register to the SCIRD buffer. The RXRDY flag therefore indicates that the SCI has new data to
be read. Receive DMA requests are enabled by the SET RX INT bit.
Parity, overrun, break detect, wake-up, and framing errors generate an error interrupt request immediately
upon detection, if enabled, even if the device is in the process of a DMA data transfer. The DMA transfer
is postponed until the error interrupt is served. The error interrupt can delete this particular DMA request
by reading the receive buffer.
In multiprocessor mode, the SCI can generate receiver interrupts for address frames and DMA requests
for data frames. This is controlled by an extra select bit SET RX DMA ALL.
If the SET RX DMA ALL bit is set and the SET RX DMA bit is set when the SCI sets the RXRDY flag, then
a receive DMA request is generated for address and data frames.
If the SET RX DMA ALL bit is cleared and the SET RX DMA bit is set when the SCI sets the RXRDY flag
upon receipt of a data frame, then a receive DMA request is generated. Receive interrupt requests are
generated for address frames.
In multiprocessor mode with the SLEEP bit set, no DMA is generated for received data frames. The
software must clear the SLEEP bit before data frames can be received. Table 29-2 specifies the bit values
for DMA requests in multiprocessor modes.
Table 29-2. DMA and Interrupt Requests in Multiprocessor Modes
SET RX DMA ADDR FRAME ADDR FRAME DATA FRAME DATA FRAME
SET RX INT SET RX DMA
ALL INT DMA INT DMA
0 0 x N N N N
0 1 0 Y N N Y
0 1 1 N Y N Y
1 0 x Y N Y N
1 1 0 Y N Y Y
1 1 1 Y Y Y Y
In multiprocessor mode, the SCI can generate receiver interrupts for address frames and DMA requests
for data frames or DMA requests for both. This is controlled by the SET RX DMA ALL bit.
In multiprocessor mode with the SLEEP bit set, no DMA is generated for received data frames. The
software must clear the SLEEP bit before data frames can be received.
29.4.2 Transmit DMA Requests
DMA functionality is enabled/disabled by the CPU with SET TX DMA/CLR TX DMA bits, respectively.
The TXRDY flag is set when the SCI transfers the contents of SCITD to SCITXSHF. The TXRDY flag
indicates that SCITD is ready to be loaded with more data. In addition, the SCI sets the TX EMPTY bit if
both the SCITD and SCITXSHF registers are empty.
1449
SPNU562–May 2014 Serial Communication Interface (SCI) Module
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