Datasheet

Address

Data

Last data

Start

Address frame

Data frame

Fewer than

10 idle bits

Idle period

One block of frames

Blocks separated by 10 or more idle bits

Blocks of frames

Data format

(pins SCIRX,

SCITX)

Data format

expanded

Stop

Data frame

Parity

SCI Communication Formats

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As indicated by Step 3, software should wait for the SCI to clear the TXWAKE bit. However, the SCI

clears the TXWAKE bit at the same time it sets TXRDY (that is, transfers data from SCITD into

SCITXSHF). Therefore, if the TX INT ENA bit is set, the transfer of data from SCITD to SCITXSHF causes

an interrupt to be generated at the same time that the SCI clears the TXWAKE bit. If this interrupt method

is used, software is not required to poll the TXWAKE bit waiting for the SCI to clear it.

When idle-line multiprocessor communications are used, software must ensure that the idle time exceeds

10 bit periods before addresses (using one of the methods mentioned above), and software must also

ensure that data frames are written to the transmitter quickly enough to be sent without a delay of 10 bit

periods between frames. Failure to comply with these conditions will result in data interpretation errors by

other devices receiving the transmission.

Figure 29-4. Idle-Line Multiprocessor Communication Format

1444

Serial Communication Interface (SCI) Module SPNU562–May 2014

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