Datasheet

Asynchronous baud value =
For BAUD = 0,
Asynchronous baud value =
VBUSPCLK Frequency
16 BAUD + 1
-----------------------------------------------------------------
VCLK Frequency
32
-------------------------------------------------
16 SCI baud clock periods/bit
Majority
vote
LSB of data
Start bit
SCIRX
Falling edge
detected
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 161 2 3 4 5
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29.2.2.1 Asynchronous Timing Mode
The asynchronous timing mode uses only the receive and transmit data lines to interface with devices
using the standard universal asynchronous receiver- transmitter (UART) protocol.
In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods. Each
bit therefore consists of 16 samples (one for each clock period). When the SCI is using asynchronous
mode, the baud rates of all communicating devices must match as closely as possible. Receive errors
result from devices communicating at different baud rates.
With the receiver in the asynchronous timing mode, the SCI detects a valid start bit if the first four samples
after a falling edge on the SCIRX pin are of logic level 0. As soon as a falling edge is detected on SCIRX,
the SCI assumes that a frame is being received and synchronizes itself to the bus.
To prevent interpreting noise as Start bit SCI expects SCIRX line to be low for at least four contiguous SCI
baud clock periods to detect a valid start bit. The bus is considered idle if this condition is not met. When a
valid start bit is detected, the SCI determines the value of each bit by sampling the SCIRX line value
during the seventh, eighth, and ninth SCI baud clock periods. A majority vote of these three samples is
used to determine the value stored in the SCI receiver shift register. By sampling in the middle of the bit,
the SCI reduces errors caused by propagation delays and rise and fall times and data line noises.
Figure 29-3 illustrates how the receiver samples a start bit and a data bit in asynchronous timing mode.
The transmitter transmits each bit for a duration of 16 SCI baud clock periods. During the first clock period
for a bit, the transmitter shifts the value of that bit onto the SCITX pin. The transmitter then holds the
current bit value on SCITX for 16 SCI baud clock periods.
Figure 29-3. Asynchronous Communication Bit Timing
29.2.2.2 Isosynchronous Timing Mode
In isosynchronous timing mode, each bit in a frame has a duration of exactly 1 baud clock period and
therefore consists of a single sample. With this timing configuration, the transmitter and receiver are
required to make use of the SCICLK pin to synchronize communication with other SCI. This mode is not
fully supported on this device because SCICLK pin is not available.
29.2.3 SCI Baud Rate
The SCI has an internally generated serial clock determined by the peripheral VCLK and the prescalers
BAUD. The SCI uses the 24-bit integer prescaler BAUD value of BRSR register to select the required
baud rates.
In asynchronous timing mode, the SCI generates a baud clock according to the following formula:
(55)
1442
Serial Communication Interface (SCI) Module SPNU562–May 2014
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