Datasheet
SCI/LIN Control Registers
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Table 28-20. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
10 TXWAKE Transmitter wakeup method select. This bit is effective in SCI mode only. The TXWAKE bit controls
whether the data in SCITD should be sent as an address or data frame using multiprocessor
communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is
cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset.
Note: TXWAKE is not cleared by the SW nRESET bit.
Address-bit mode
0 Frame to be transmitted will be data (address bit = 0).
1 Frame to be transmitted will be an address (address bit = 1).
Idle-line mode
0 The frame to be transmitted will be data.
1 The following frame to be transmitted will be an address (writing a 1 to this bit followed by writing
dummy data to the SCITD will result in a idle period of 11 bit periods before the next frame is
transmitted).
9 RXRDY Receiver ready flag. In SCI-compatible mode, the receiver sets this bit to indicate that the SCIRD
contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid
frame is received in multi-buffer mode, a valid frame being a message frame received with no
errors. In non-multi-buffer mode, RXRDY is set for each received byte and will be set for the last
byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY
flag bit is set if the interrupt-enable bit is set (SCISETINT[9]); RXRDY is cleared by the following:
• Setting of the SW nRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the SCIRD register in compatibility mode
• Reading the last data byte RDy of the response in LIN mode
Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
0 Read: No new data is in SCIRD.
Write: No effect.
1 Read: New data is ready to be read from SCIRD.
Write: The bit is cleared to 0.
8 TXRDY Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s)
register(s) (SCITD in compatibility mode and LINTD0/LINTD1 in multi-buffer mode) are ready to get
another character from a CPU write.
In SCI, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte
0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer is shifted into the
SCITXSHF register. This event can trigger a transmit interrupt after data is copied to the TX shift
register SCITXSHF, if the interrupt enable bit TXINT is set.
Note:
1) TXRDY is also set to 1 either by setting of the RESET bit, enabling SW nRST or by a
system reset.
2) The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
3) The transmit interrupt request can be eliminated until the next series of data written into
the transmit buffers LINTD0 and LINTD1, by disabling the corresponding interrupt via the
SCICLEARINT register or by disabling the transmitter via the TXENA bit.
SCI mode
0 SCITD is full.
1 SCITD is ready to receive the next character.
LIN mode
0 The multi-buffers are full.
1 The multi-buffers are ready to receive the next character(s).
For more information on transmit interrupt handling, see the SCI document for compatibility mode
and Section 28.3.1.9 for LIN mode.
1412
Serial Communication Interface (SCI)/Local Interconnect Network (LIN) SPNU562–May 2014
Module
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