Datasheet

www.ti.com SCI/LIN Control Registers
28.7.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL)
Figure 28-34 and Table 28-19 illustrate this register.
Figure 28-34. SCI Clear Interrupt Level Register (SCICLEARINTLVL) (offset = 18h)
31 30 29 28 27 26 25 24
CLR BE CLR PBE CLR CE CLR ISFE CLR NRE CLR FE CLR OE CLR PE
INT LVL INT LVL INT LVL INT LVL INT LVL INT LVL INT LVL INT LVL
R/WL-0 R/WL-0 R/WL-0 R/WL-0 R/WL-0 R/W-0 R/W-0 R/W-0
23 19 18 17 16
CLR RX DMA
Reserved Reserved
ALL INT LVL
R-0 R/WC-0 R-0
15 14 13 12 10 9 8
CLR ID CLR RX CLR TX
Reserved Reserved
INT LVL INT LVL INT LVL
R-0 R/WL-0 R-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CLR
CLR TOAWUS CLR TIMEOUT CLR WAKEUP CLR BRKDT
TOA3WUS Reserved Reserved
INT LVL INT LVL INT LVL INT LVL
INT LVL
R/WL-0 R/WL-0 R-0 R/WL-0 R-0 R/W-0 R/WC-0
LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset
Table 28-19. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions
Bit Field Value Description
31 CLR BE INT LVL Clear bit error interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
30 CLR PBE INT LVL Clear physical bus error interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
29 CLR CE INT LVL Clear checksum-error interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
28 CLR ISFE INT LVL Clear inconsistent-synch-field-error (ISFE) interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
27 CLR NRE INT LVL Clear no-response-error interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
1405
SPNU562–May 2014 Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
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